This invention relates generally to memory devices, and more particularly to a method and apparatus for reducing the access time necessary to read data out of a memory device, such as a dynamic random access memory (DRAM) device, a synchronous DRAM (SDRAM) device, or the like.
In a recent memory device, a power supply voltage VCC becomes lower to, for example, 3.3 V. A row decoder needs to use a voltage, which has a higher level than the threshold level Vth of the storage cell, on driving a selected wordline. The higher level voltage is referred to as xe2x80x9ca selection level voltagexe2x80x9d and belongs to a range, for example, between 4 V and 5 V.
In order to supply the row decoder with the higher level voltage, DRAM devices or SDRAM devices commonly use a booting circuit that can produce a booted or boosted voltage which has a voltage level higher than a power supply voltage VCC.
However, the booted voltage declines in voltage level when the row decoder drives the selected wordline, because the booted voltage is temporally consumed in driving the selected wordline. The temporal consumption of the booted voltage may result in that the booted voltage falls below the selection level voltage, and that the drive of the wordline is unstable. To ensure the readout operation, it is necessary that the booted voltage recovers its level and reaches the selection level voltage. Hence, the memory access time for the stable readout operation is often excessive in previously developed memory device.
It is therefore an object of the present invention to provide an improved memory device which can reduce the memory access time in comparison with the previously developed memory device.
Generally, when a /RAS (/ row address strobe) signal is input to a memory device, a control logic of the memory device issues an internal /RAS signal corresponding to the /RAS signal and then a row decoder drives a selected wordline in response to the internal /RAS signal. It is noted here that a predetermined time internal passes from the issue of the internal /RAS signal to the drive of the selected wordline, depending upon a circuit layout of the memory device, skew and so forth. One aspect of the present invention utilizes the predetermined time interval for a time of pre-booting at a booting circuit.
According to one aspect of the present invention, a memory device includes a memory cell array, a control logic, a booting circuit, and a row decoder. The memory cell array comprises storage cells organized and connected to wordlines and bitlines in rows and columns. The control logic issues an internal /RAS signal in response to a /RAS signal input to the memory device.
The booting circuit is coupled to the control logic and the row decoder. The booting circuit produces as a booted voltage signal a voltage which is booted to a selection level voltage in normal and which is further booted above the selection level voltage when the internal /RAS signal starts to turn on. Herein, the selection level voltage is a voltage necessary to drive the wordline. The booted voltage signal is delivered to the row decoder from the booting circuit.
The row decoder is coupled to the control logic and connected to the wordlines. The row decoder starts to drive a selected one of the wordlines with the booted voltage signal when a predetermined time interval passes since the internal /RAS signal starts to turn on. For example, the predetermined time interval depends on a circuit layout of the memory device.
With the above structure, the booted voltage is further booted above the selection level voltage before the row decoder drives the selected wordline. Even if the booted voltage signal declines in voltage level when being temporally consumed in driving the selected wordline, the probability that the booted voltage signal falls below the selection level voltage is decreased. In addition, if falling below the selection level voltage, the booted voltage signal can recover its level and can reach the selection level voltage with a shorter time. Therefore, the memory access time for the stable readout operation is reduced in the memory device according to one aspect of the present invention.
These and other aspects of the present invention, as well as its advantages and features are described as preferred embodiments in more detail in conjunction with the text below and attached figures.